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HT1625
RAM Mapping 648 LCD Controller for I/O MCU
PATENTED
PAT No. : 099352
Technical Document
* Application Note
Features
* Operating voltage: 2.7V~5.2V * Built-in RC oscillator * External 32.768kHz crystal or 32kHz frequency * Built-in LCD display RAM * R/W address auto increment * Two selectable buzzer frequencies (2kHz or 4kHz) * Power down command reduces power consumption * Software configuration feature * Data mode and Command mode instructions * Three data accessing modes * VLCD pin to adjust LCD operating voltage * 100-pin QFP package
source input
* 1/4 bias, 1/8 duty, frame frequency is 64Hz * Max. 648 patterns, 8 commons, 64 segments * Built-in internal resistor type bias generator * 3-wire serial interface * 8 kinds of time base or WDT selection * Time base or WDT overflow output
General Description
HT1625 is a peripheral device specially designed for I/O type MCU used to expand the display capability. The max. display segment of the device are 512 patterns (648). It also supports serial interface, buzzer sound, Watchdog Timer or time base timer functions. The HT1625 is a memory mapping and multi-function LCD controller. The software configuration feature of the HT1625 make it suitable for multiple LCD applications including LCD modules and display subsystems. Only three lines are required for the interface between the host controller and the HT1625. The HT162X series have many kinds of products that match various applications.
Selection Table
HT162X COM SEG Built-in Osc. Crystal Osc. HT1620 4 32 3/4 O HT1621 4 32 O O HT1622 8 32 O 3/4 HT16220 8 32 3/4 O HT1623 8 48 O O HT1625 8 64 O O HT1626 16 48 O O
Rev. 1.40
1
June 12, 2009
PATENTED
Block Diagram
HT1625
OSCO OSCI CS RD WR DATA VDD VSS BZ BZ T o n e F re q u e n c y G e n e ra to r Con an T im C ir c tro l d in g u it
D is p la y R A M
COM0 L C D D r iv e r / B ia s C ir c u it COM7 SEG0 SEG 63 VLCD W a tc h d o g T im e r and T im e B a s e G e n e r a to r IR Q
Pin Assignment
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 WR DATA VSS OSCI OSCO VDD VLC D IR Q BZ BZ T1 T2 T3 NC COM0 COM1 COM2 COM3 NC NC NC NC COM4 NC COM5 NC COM6 NC
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 4445 46 4748 49 50
CS RD
1 2
100 99 98 97 96 9594 93 92 91 90 89 88 87 86 8584 83 82 81
63
62
61
60
59
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
H T1625 1 0 0 Q F P -A
SE NC SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE NC NC SE SE SE SE
G 43 G4 G4 G4 G3 G3 G3 G3 G3 G3 G3 G3 G3 G3 G2 G2 G2 G2 G2 G2 G2 G2 G2 7 4 3 2 1 5 6 G2 G1 G1 G1 9 1 0 9 2
8
9
0
1
2
3
4
5
6
7
8
0 8 7
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG NC NC COM 16 15 14 13 12 11 10 9 6 3 1 0 2 4 7 5 7 8
Rev. 1.40
2
June 12, 2009
PATENTED
Pad Assignment
SEG 63
86
HT1625
SEG 62
85
SEG 61
SEG 60
SEG 59
SEG 58
SEG 57
SEG 56
SEG 55
SEG 54
SEG 53
SEG 52
SEG 51
SEG 50
SEG 49
SEG 48
SEG 47
SEG 46
SEG 45
SEG 44
SEG 43
CS
87 1 2 3 4
RD WR DATA VSS
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65 64 63 62
SEG 42 SEG 41 SEG 40 SEG 39 SEG 38 SEG 37 SEG 36 SEG 35 SEG 34 SEG 33 SEG 32 SEG 31 SEG 30 SEG 29 SEG 28 SEG 27 SEG 26 SEG 25 SEG 24 SEG 23 SEG 22 SEG 21 SEG 20
OSCI
5 6 7 8 9
61 60 59 58 57 56 (0 , 0 ) 55 54 53 52 51 50 49 48 47 46 45
OSCO VDD VLCD IR Q BZ BZ T1 T2 T3 COM0 COM1 COM2 COM3
10 11 12 13 14 15 16 17 18
COM4
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
44 43
COM5
COM6
* The IC substrate should be connected to VDD in the PCB layout artwork.
COM7
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
Chip size: 118 128 (mil)2
SEG6
SEG7
SEG8
SEG9
SEG 10
SEG 11
SEG 12
SEG 13
SEG 14
SEG 15
SEG 16
SEG 17
SEG 18
SEG 19
Rev. 1.40
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June 12, 2009
PATENTED
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 X -1399.087 -1399.087 -1399.087 -1399.087 -1399.087 -1399.087 -1399.087 -1399.087 -1399.087 -1400.132 -1400.132 -1400.132 -1400.132 -1400.132 -1400.132 -1400.132 -1400.132 -1400.132 -1400.132 -1254.633 -1155.531 -1056.513 -957.411 -858.392 -759.292 -660.272 -561.172 -462.153 -363.052 -264.033 -164.932 -65.912 33.188 132.208 231.309 330.328 429.159 614.539 713.638 899.018 998.119 1183.499 1396.978 1396.978 Y 1514.994 1415.973 1316.263 1140.800 876.062 684.333 585.273 486.214 387.114 237.773 87.535 -53.536 -152.637 -251.656 -350.758 -449.776 -548.878 -647.896 -1401.530 -1523.957 -1523.957 -1523.957 -1523.957 -1523.957 -1523.957 -1523.957 -1523.957 -1523.957 -1523.957 -1523.957 -1523.957 -1523.957 -1523.957 -1523.957 -1523.957 -1523.957 -1523.957 -1523.957 -1523.957 -1523.957 -1523.957 -1523.957 -1525.401 -1426.302 Pad No. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 X 1396.978 1396.978 1396.978 1396.978 1396.978 1396.978 1396.978 1396.978 1396.978 1396.978 1396.978 1396.978 1396.978 1396.978 1396.978 1396.978 1396.978 1396.978 1396.978 1396.978 1364.057 1172.328 1073.228 881.497 782.397 590.667 485.994 386.972 287.874 188.852 89.753 -9.267 -108.367 -207.387 -306.487 -405.508 -504.607 -603.628 -702.727 -801.747 -900.846 -999.868 -1098.967
HT1625
Unit: mm Y -1327.281 -1228.182 -1082.807 -983.707 -798.327 -699.227 -513.846 -414.747 -229.367 -130.266 55.114 154.214 339.594 438.693 624.073 723.173 908.553 1007.654 1193.033 1292.134 1521.618 1521.618 1521.618 1521.618 1521.618 1521.618 1521.618 1521.618 1521.618 1521.618 1521.618 1521.618 1521.618 1521.618 1521.618 1521.618 1521.618 1521.618 1521.618 1521.618 1521.618 1521.618 1521.618
Rev. 1.40
4
June 12, 2009
PATENTED
Pad Description
Pad No. Pad Name I/O Description
HT1625
1
RD
I
READ clock input with pull-high resistor. Data in the RAM of the HT1625 are clocked out on the falling edge of the RD signal. The clocked out data will appear on the data line. The host controller can use the next rising edge to latch the clocked out data. WRITE clock input with pull-high resistor. Data on the DATA line are latched into the HT1625 on the rising edge of the WR signal. Serial data input or output with pull-high resistor Negative power supply, ground The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to generate a system clock. If the system clock comes from an external clock source, the external clock source should be connected to the OSCI pad. But if an on-chip RC oscillator is selected instead, the OSCI and OSCO pads can be left open. Positive power supply LCD operating voltage input pad. Time base or Watchdog Timer overflow flag, NMOS open drain output 2kHz or 4kHz tone frequency output pair Not connected LCD common outputs LCD segment outputs Chip selection input with pull-high resistor. When the CS is logic high, the data and command read from or write to the HT1625 are disabled. The serial interface circuit is also reset. But if the CS is at logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT1625 are all enabled.
2 3 4 5
WR DATA VSS OSCI
I I/O 3/4 I
6
OSCO
O 3/4 I O O I O O
7 8 9 10, 11 12~14 15~22 23~86
VDD VLCD IRQ BZ, BZ T1~T3 COM0~COM7 SEG0~SEG63
87
CS
I
Absolute Maximum Ratings
Supply Voltage .........................................-0.3V to 5.5V Input Voltage.............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...........................-25C to 75C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.40
5
June 12, 2009
PATENTED
D.C. Characteristics
Symbol VDD IDD1 IDD2 IDD11 IDD22 ISTB VIL VIH IOL1 IOH1 IOL1 IOH1 IOL2 IOH2 IOL3 IOH3 RPH Parameter Operating Voltage Operating Current Test Conditions VDD 3/4 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V Conditions 3/4 No load or LCD ON On-chip RC oscillator No load or LCD ON Crystal oscillator No load or LCD OFF On-chip RC oscillator No load or LCD OFF Crystal oscillator No load, Power down mode Min. 2.7 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0 2.4 4.0 0.9 1.7 -0.9 -1.7 0.9 1.7 -0.9 -1.7 80 180 -40 -90 50 120 -30 -70 100 50 Typ. 3/4 155 260 150 250 8 20 3/4 3/4 1 2 3/4 3/4 3/4 3/4 1.8 3 -1.8 -3 1.8 3 -1.8 -3 160 360 -80 -180 100 240 -60 -140 200 100
HT1625
Ta=25C Max. 5.2 310 420 310 420 30 60 20 35 12 24 0.6 1.0 3 5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 300 150 Unit V mA mA mA mA mA mA mA mA mA mA V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA kW kW
Operating Current
Operating Current
Operating Current
Standby Current
Input Low Voltage
DATA, WR, CS, RD
Input High Voltage
DATA, WR, CS, RD VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V DATA, WR, CS, RD
BZ, BZ, IRQ
BZ, BZ
DATA
DATA
LCD Common Sink Current
LCD Common Source Current
LCD Segment Sink Current
LCD Segment Source Current
Pull-high Resistor
A.C. Characteristics
Symbol fSYS1 fSYS2 fLCD1 fLCD2 Parameter System Clock System Clock LCD Frame Frequency LCD Frame Frequency Test Conditions VDD 5V 3/4 5V 3/4 Conditions On-chip RC oscillator External clock source On-chip RC oscillator External clock source Min. 24 3/4 48 3/4 Typ. 32 32 64 64 Max. 40 3/4 80 3/4
Ta=25C Unit kHz kHz Hz Hz
Rev. 1.40
6
June 12, 2009
PATENTED
Symbol tCOM fCLK1 fCLK2 tCS Parameter LCD Common Period Serial Data Clock (WR Pin) Test Conditions VDD 3/4 3V 5V 3V 5V 3/4 3V tCLK WR, RD Input Pulse Width (Figure 1) 5V t r, t f tsu th tsu1 th1 ftone tOFF tSR Note: Rise or Fall Time Serial Data Clock Width (Figure 1) Setup Time for DATA to WR, RD Clock Width (Figure 2) Hold Time for DATA to WR, RD Clock Width (Figure 2) Setup Time for CS to WR, RD Clock Width (Figure 3) Hold Time for CS to WR, RD Clock Width (Figure 3) Tone Frequency (2KHz) Tone Frequency (4KHz) VDD OFF Times (Figure 4) VDD Rising Slew Rate (Figure 4) 3/4 3/4 3/4 3/4 3/4 5V 3/4 3/4 Conditions n: Number of COM Duty cycle 50% Min. 3/4 4 4 3/4 3/4 700 3.34 6.67 1.67 3.34 3/4 60 700 500 50 1.5 3.0 20 0.05 Typ. n/fLCD 3/4 3/4 3/4 3/4 800 3/4 3/4 3/4 3/4 120 120 800 600 100 2.0 4.0 3/4 3/4
HT1625
Max. 3/4 150 300 75 150 3/4 125 3/4 125 3/4 160 3/4 3/4 3/4 3/4 2.5 5.0 3/4 3/4 Unit sec kHz kHz kHz kHz ns ms ms ns ns ns ns ns kHz kHz ms V/ms
Serial Data Clock (RD Pin) Serial Interface Reset Pulse Width (Figure 3)
Duty cycle 50% CS Write mode Read mode Write mode Read mode 3/4 3/4 3/4 3/4 3/4 On-chip RC oscillator VDD drop down to 0V 3/4
1. If the conditions of Power-on Reset timing are not satisfied in power On/Off sequence, the internal Power-on Reset (POR) circuit will not operate normally. 2. If the VDD drops below the minimum voltage of operating voltage spec. during operating, the conditions of Power-on Reset timing must be satisfied also. That is, the VDD must drop to 0V and keep at 0V for 20ms (min.) before rising to the normal operating voltage.
V A L ID D A T A
tf W R,RD C lo c k 90% 50% 10%
tr V tC
LK
DD
DB
50% ts
u
V th V
DD
GND
DD
tC
GND
W R,RD C lo c k
LK
50%
GND
Figure 1
Figure 2
tC
S
CS
50% ts
u1
V
DD
th
1
GND V
DD
VDD
W R,RD C lo c k
0V
tS
R
50% F IR S T C lo c k
tO
FF
LAST C lo c k
GND
Figure 3
Figure 4 Power-on Reset Timing
Rev. 1.40
7
June 12, 2009
PATENTED
Functional Description
Display memory - RAM structure The static display RAM is organized into 1284 bits and stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessed by the READ, WRITE and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD patterns. Time base and Watchdog Timer - WDT The time base generator and WDT share the same divided (/256) counter. TIMER DIS/EN/CLR , WDT DIS/EN/CLR and IRQ EN/DIS are independent from each other. Once the WDT time-out occurs, the IRQ pin will remain at logic low level until the CLR WDT or the IRQ DIS command is issued.
COM7 SEG0 SEG1 SEG2 SEG3 7 5 6 3 4 COM6 COM5 COM4 1 2 COM3
HT1625
If an external clock is selected as the source of system frequency, the SYS DIS command turns out invalid and the power down mode fails to be carried out until the external clock source is removed. Buzzer tone output A simple tone generator is implemented in the HT1625. The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate a single tone. Command format The HT1625 can be configured by the software setting. There are two mode commands to configure the HT1625 resource and to transfer the LCD display data.
COM2 COM1 COM0 0
A d d r e s s 7 B its (A 6 , A 5 , ...., A 0 )
SEG 63 D3 D2 D1 D0
127 Addr D a ta D3 D2 D1 D0
126 Addr D a ta
D a ta 4 B its (D 3 , D 2 , D 1 , D 0 )
RAM mapping
T im e B a s e C lo c k S o u r c e /2 5 6 V C L R T im e r
DD
T IM E R E N /D IS W D T E N /D IS D CK R Q IR Q E N /D IS
IR Q
W DT /4
CLR
W DT
Timer and WDT configurations
Rev. 1.40
8
June 12, 2009
PATENTED
The following are the data mode ID and the command mode ID: Operation READ WRITE READ-MODIFY-WRITE COMMAND Name TONE OFF TONE 4K TONE 2K Mode Data Data Data Command Command Code 0000-1000-X 010X-XXXX-X 0110-XXXX-X Turn-off tone output Turn-on tone output, tone frequency is 4kHz Turn-on tone output, tone frequency is 2kHz ID 110 101 101 100 Function
HT1625
If successive commands have been issued, the command mode ID can be omitted. While the system is operating in the non-successive command or the non-successive address data mode, the CS pin should be set to 1 and the previous operation mode will be reset also. The CS pin returns to 0, a new operation mode ID should be issued first.
Timing Diagrams
READ mode (command code : 1 1 0)
CS
WR
RD
DATA
1 1
0
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3 1
1
0
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
M e m o ry A d d re s s 1 (M A 1 )
D a ta (M A 1 )
M e m o ry A d d re s s 2 (M A 2 )
D a ta (M A 2 )
READ mode (successive address reading)
CS
WR
RD
DATA
1 1
0
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
M e m o ry A d d re s s (M A )
D a ta (M A )
D a ta (M A + 1 )
D a ta (M A + 2 )
D a ta (M A + 3 )
Rev. 1.40
9
June 12, 2009
PATENTED
WRITE mode (command code : 1 0 1)
CS
HT1625
WR
DATA
1 0
1
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3 1
0
1
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
M e m o ry A d d re s s 1 (M A 1 )
D a ta (M A 1 )
M e m o ry A d d re s s 2 (M A 2 )
D a ta (M A 2 )
WRITE mode (successive address writing)
CS
WR
DATA
1 0
1
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
M e m o ry A d d re s s (M A )
D a ta (M A )
D a ta (M A + 1 )
D a ta (M A + 2 )
D a ta (M A + 3 )
READ-MODIFY-WRITE mode (command code : 1 0 1)
CS
WR
RD
DATA
1 0
1
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
D0
D1
D2
D3 1
0
1
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
M e m o ry A d d re s s 1 (M A 1 )
D a ta (M A 1 )
D a ta (M A 1 )
M e m o ry A d d re s s 2 (M A 2 )
D a ta (M A 2 )
READ-MODIFY-WRITE mode (successive address accessing)
CS
WR
RD
DATA
1 0
1
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
M e m o ry A d d re s s (M A )
D a ta (M A )
D a ta (M A )
D a ta (M A + 1 )
D a ta (M A + 1 )
D a ta (M A + 2 )
Rev. 1.40
10
June 12, 2009
PATENTED
Command mode (command code : 1 0 0)
CS
HT1625
WR
DATA
1 0
0
C8
C7
C6
C5
C4
C3
C2
C1
C0
C8 C o m m a n d ...
C7
C6
C5
C4
C3
C2
C1
C0 Com m and or D a ta M o d e
Com m and 1
Com m and i
Mode (data and command mode)
CS
WR
DATA Com m and or D a ta M o d e RD A d d re s s a n d D a ta Com m and or D a ta M o d e A d d re s s a n d D a ta Com m and or D a ta M o d e A d d re s s a n d D a ta
Rev. 1.40
11
June 12, 2009
PATENTED
Application Circuits
HT1625
*
MCU
*R
CS RD WR DATA VDD *V R VLCD BZ P ie z o BZ COM0~COM7 SEG 0~SEG 63
H T1625
IR Q OSCI C lo c k O u t E x te r n a l C lo c k 1 ( 3 2 k H z ) E x te r n a l C lo c k 2 ( 3 2 k H z ) O n - c h ip O S C 1 /4 B ia s , 1 /8 D u ty OSCO
LCD
C ry s ta l 32768H z
Panel
Note:
The connection of IRQ and RD pin can be selected depending on the requirement of the MCU. The voltage applied to VLCD pin must be lower than VDD. Adjust VR to fit LCD display, at VDD=5V, VLCD=4V, VR=15kW20%. Adjust R (external Pull-high resistance) to fit users time base clock.
Instruction Set Summary
Name READ WRITE ID Command Code D/C D D D C C C C C C C C C C C C C Function Read data from the RAM Write data to the RAM Read and Write data to the RAM Turn off both system oscillator and LCD bias generator Turn on system oscillator Turn off LCD display Turn on LCD display Disable time base output Disable WDT time-out flag output Enable time base output Enable WDT time-out flag output Turn off tone outputs Clear the contents of the time base generator Clear the contents of the WDT stage System clock source, on-chip RC oscillator System clock source, external 32kHz clock source or crystal oscillator 32.768kHz Yes Yes Yes Yes Yes Yes Def. 1 1 0 A6A5A4A3A2A1A0D0D1D2D3 1 0 1 A6A5A4A3A2A1A0D0D1D2D3
READ-MODIFY1 0 1 A6A5A4A3A2A1A0D0D1D2D3 WRITE SYS DIS SYS EN LCD OFF LCD ON TIMER DIS WDT DIS TIMER EN WDT EN TONE OFF CLR TIMER CLR WDT RC 32K 1 0 0 0000-0000-X 1 0 0 0000-0001-X 1 0 0 0000-0010-X 1 0 0 0000-0011-X 1 0 0 0000-0100-X 1 0 0 0000-0101-X 1 0 0 0000-0110-X 1 0 0 0000-0111-X 1 0 0 0000-1000-X 1 0 0 0000-1101-X 1 0 0 0000-1111-X 1 0 0 0001-10XX-X
EXT (XTAL) 32K 1 0 0 0001-11XX-X
Rev. 1.40
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June 12, 2009
PATENTED
Name TONE 4K TONE 2K IRQ DIS IRQ EN F1 F2 F4 F8 F16 F32 F64 F128 TEST NORMAL Note: ID Command Code D/C C C C C C C C C C C C C C C Function Tone frequency output: 4kHz Tone frequency output: 2kHz Disable IRQ output Enable IRQ output Time base clock output: 1Hz The WDT time-out flag after: 4s Time base clock output: 2Hz The WDT time-out flag after: 2s Time base clock output: 4Hz The WDT time-out flag after: 1s Time base clock output: 8Hz The WDT time-out flag after: 1/2s Time base clock output: 16Hz The WDT time-out flag after: 1/4s Time base clock output: 32Hz The WDT time-out flag after: 1/8s Time base clock output: 64Hz The WDT time-out flag after: 1/16s Time base clock output: 128Hz The WDT time-out flag after: 1/32s Test mode, user dont use. Normal mode 1 0 0 010X-XXXX-X 1 0 0 0110-XXXX-X 1 0 0 100X-0XXX-X 1 0 0 100X-1XXX-X 1 0 0 101X-0000-X 1 0 0 101X-0001-X 1 0 0 101X-0010-X 1 0 0 101X-0011-X 1 0 0 101X-0100-X 1 0 0 101X-0101-X 1 0 0 101X-0110-X 1 0 0 101X-0111-X 1 0 0 1110-0000-X 1 0 0 1110-0011-X
HT1625
Def.
Yes
Yes
Yes
X : Dont care A6~A0 : RAM address D3~D0 : RAM data D/C : Data/Command mode Def. : Power on reset default All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The source of the tone frequency and of the time base or WDT clock frequency can be derived from an on-chip 32kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 32kHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1625 after power on reset, for power on reset may fail, which in turn leads to the malfunctioning of the HT1625.
Rev. 1.40
13
June 12, 2009
PATENTED
Package Information
100-pin QFP (14mm20mm) Outline Dimensions
HT1625
C D 80 51 G H
I 81 50
F A B
E
100
31 K 1 30 = J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 18.50 13.90 24.50 19.90 3/4 3/4 2.50 3/4 3/4 1 0.10 0 Nom. 3/4 3/4 3/4 3/4 0.65 0.30 3/4 3/4 0.10 3/4 3/4 3/4 Max. 19.20 14.10 25.20 20.10 3/4 3/4 3.10 3.40 3/4 1.40 0.20 7
Rev. 1.40
14
June 12, 2009
PATENTED
HT1625
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) G Room, 3 Floor, No.1 Building, No.2016 Yi-Shan Road, Minhang District, Shanghai, China 201103 Tel: 86-21-5422-4590 Fax: 86-21-5422-4705 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2008 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.40
15
June 12, 2009

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